Bit Greater than Comparator 1. Create a 2-Bit Comparator schematic that produces a logic high output when a 2-bit number A is greater than a 2-bit number B a. Label inputs as A1 as the MSB, and A0 as the LSB. b. Label inputs as B1 as the MSB, and B0 as the LSB. 2. Use Pulsed Voltage sources to create 3 input signal cases: a. 1 case where A>B b. 1 case where A=B c. 1 case where A<B 3. Create Waveform Plots of Inputs and the Outputs of the circuit. 4. Capture the Schematic, the input signals and the output signals for each gate.
The Correct Answer and Explanation is:
1. Logic Function and Schematic Design
Inputs:
- A1 (Most Significant Bit of A)
- A0 (Least Significant Bit of A)
- B1 (Most Significant Bit of B)
- B0 (Least Significant Bit of B)
Output:
- A_GT_B (High when A > B)
Logic Equation:
A_GT_B = (A1 AND NOT B1)
OR (A1 XNOR B1 AND A0 AND NOT B0)
This logic checks if the MSB of A is greater than B. If the MSBs are equal, it checks the LSB.
2. Input Signal Cases Using Pulsed Voltage Sources
| Case | A1 | A0 | B1 | B0 | Condition |
|---|---|---|---|---|---|
| 1 | 1 | 0 | 0 | 1 | A > B |
| 2 | 0 | 1 | 0 | 1 | A = B |
| 3 | 0 | 1 | 1 | 0 | A < B |
Each input bit should be driven by a pulsed voltage source configured to alternate between 0 V and 5 V with suitable timing to display the three conditions above in sequence.
3. Waveform Plots
Plot the waveforms of all inputs (A1, A0, B1, B0) and the output (A_GT_B). You should observe:
- A_GT_B = High only during the A > B condition.
- Low during A = B and A < B.
4. Captures
Capture:
- The schematic showing the gate-level design (AND, OR, NOT, XNOR).
- Input signal plot showing transitions for each bit.
- Output signal plot showing A_GT_B high when appropriate.
Explanation
A 2-bit comparator evaluates which of two binary numbers is greater. For this design, each number is represented using two inputs: A1 A0 for number A and B1 B0 for number B. The comparison follows binary weight, where A1 and B1 hold more significance than the lower bits.
The comparator operates in hierarchical logic. It first checks the most significant bits (A1 and B1). If A1 is 1 while B1 is 0, then clearly A is greater than B regardless of the LSBs. This condition is captured using the term (A1 AND NOT B1).
However, if A1 equals B1, we must compare the LSBs. This equality is tested using an XNOR gate. If A1 and B1 are the same, and A0 is 1 while B0 is 0, then again A is greater than B. This condition is expressed by (A1 XNOR B1) AND (A0 AND NOT B0).
Combining both scenarios with an OR gate ensures that the output A_GT_B is high precisely when A is greater than B. By using pulsed voltage sources, we simulate three key scenarios for validation. The waveforms visually confirm that the logic behaves as expected, transitioning the output high only under the correct circumstances.
This setup is foundational in digital logic systems, especially useful in decision-making circuits, CPUs, and sorting hardware.
